1. Field of the Invention
In digital circuits, it is oftentimes necessary to determine the timing of the edges of different signals relative to one another. If a pulse is generated with an edge that must have a predefined timing, which is to say a predetermined time relationship (for example, a delay) relative to a rising or falling edge of a clock signal, then it is important to verify whether the edge of the pulse actually has this predefined timing.
2. Description of the Background Art
Known from US 2003/0006750 A1 is a measurement component for time measurement with a Vernier delay line (VDL). To this end, two delay lines having different fixed delay times are provided, each of which is fed back to produce an oscillator. As a result of slightly differing frequencies of the two oscillators, a time difference between an edge of a data signal and an edge of a clock signal can be measured using a count of the oscillations. Process-related differences in the delay elements can be eliminated with the production of identical delay elements in each stage.